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|Title: ||A 5 GHz integrated low-power CMOS RF front-end IC design|
|Authors: ||Tsui, Hau Yiu|
|Issue Date: ||2004 |
|Abstract: ||The continued improvement in CMOS transistor speed has prompted many to look into the possibility of building fully integrated RF front-end circuits using the low-cost and commercially available standard CMOS process. Direct conversion architecture offers the potential benefit of low-cost and low-power consumption for the transceiver circuit. It requires minimum components operating at the RF frequency. The circuit design is much simpler due to the absence of the image rejection requirement. However, since the received signal is only processed at two frequencies: RF and baseband, its sensitivity and dynamic range will be limited by the insufficient signal amplification, noise and interference suppression at the RF stage, and the large DC-offset and flicker noise at the baseband stage. Furthermore, for fully integrated transceiver circuits, their performance are still limited by the missing on-chip high-quality band- or channel-selection filter at the RF stage which is used to replace the bulky and expensive off-chip SAW filter.
In this thesis, low-power high-performance RF front-end circuits were implemented using a 0.18 μm 6-metal layer CMOS process to address the limitation of the direct conversion receiver. A 5 GHz, 56 dB voltage-gain Low Noise Amplifier (LNA) with built-in tunable 30 MHz channel-selection filter was designed which helps to minimize the impact of the DC-offset and flicker noise on the sensitivity of the direct conversion receiver. The LNA drains 0.9 mA current from the 1.5 V power supply and has 6.5 dB noise figure. A very low power-consumption 5 GHz Voltage Controlled Oscillator (VCO) was also designed which has 10% tuning range. The phase noise is -106 dBc/Hz at 1 MHz offset while the VCO core drains 0.5 mA current from the 1 V power supply. The high performance and low power-consumption of above fully integrated circuits rely on the using of high-quality on-chip inductors. A compact 3-dimensional vertical solenoid inductor structure was proposed for the CMOS on-chip inductor design. Compared to the 4.1 nH conventional circular planar spiral inductor fabricated on the same chip, the 4.8 nH solenoid inductor gives about 20% improvement in the maximum quality-factor and 50% increase in the self-resonant frequency, but only occupies 20% of the die area.|
|Description: ||Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2004|
viii, 101 leaves : ill. ; 30 cm
HKUST Call Number: Thesis ELEC 2004 Tsui
|Appears in Collections:||ECE Doctoral Theses|
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