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Title: Design and integration of a single-chip low-power single-coversion CMOS cable TV tuner
Authors: Wang, Dan
Issue Date: 2005
Abstract: There has been an increasing demand for cheaper, smaller, higher-performance tuners for consumer digital television set top boxes, integrated digital TVs, and mobile devices. At present, highly integrated cable TV systems employ either single-conversion architecture or dual-conversion architecture to avoid using high-Q RF tracking filters. The single-conversion architecture is quite simple, only LNA and image-reject mixer are used in the RF front-end. The wide band (50-860 MHz) input is directly downconverted to IF (44MHz). However, in the dual-conversion architecture, the input is first upconverted to some high frequency such as 1.22GHz, then is downconverted to IF (44Hz); it includes the LNA, the up-conversion mixer, the band-pass filter and the down-conversion mixer. Both architectures have advantages and disadvantages, which will be discussed later. In this dissertation, an analog integrated single-conversion tuner for cable modem applications in a pure 0.18-μm CMOS process with 1.8-V supply is introduced which is designed by our cable tuner group. The tuner integrates the whole single-conversion, low-IF signal path including low noise amplifier, image-reject mixer, wide-band VCO driving an integer-N phase locked loop with an on-chip forth-order dual-path loop filter and high-attenuation channel -selection filter. It downconverts wide-band input (50MHz-860MHz) to 44MHz and achieves 70-dB gain (maximum), 54.5-dB gain control range, 8.7-dB noise figure, 7.5-dBm IIP3, -53.8-dBc composite triple beat (CTB), -54.3-dBc composite second order (CSO), 63-dB image rejection ratio and 60-dB adjacent channel rejection.
Description: Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2005
xvi, 195 leaves : ill. ; 30 cm
HKUST Call Number: Thesis ELEC 2005 Wang
Appears in Collections:ECE Doctoral Theses

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