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|Title: ||Three dimensional multi-gates devices and circuits fabrication, characterization, and modeling|
|Authors: ||Wu, Xu Sheng|
|Issue Date: ||2005 |
|Abstract: ||To continue the scaling of CMOS technology to 65 nm node and beyond, FinFET double-gate device structure is generally considered to be the most promising candidate because of its super short channel property. The fabrication, characterization, and modeling of FinFETs become more and more important considering its strategic status. To further increase circuit performance and density, three-dimensional integrated circuit has been proposed as potential candidate. The implementation and study of 3-D ICs are also very important for future IC generations.
In our work, a FinFET technology is developed to implement double gate device. By using Capped Trimming Hard-mask method and ICP DRIE system, vertical sub-50 nm fins were fabricated based on 0.5 μm technology. The process is further simplified through optimizing the layout design. The fabricated FinFET devices are studied for radio frequency property and characteristics under irradiation environment. The impacts of non-vertical sidewall in the fin structures on the electrical performance of FinFET devices are evaluated by 3-D device simulation. I-V characteristics & fin height relationship becomes more complicated and the short channel effect immunity of a FinFET structure will also be affected. Considering such effects, three-dimension models have been developed to predict the electrical properties of FinFET. Using existing design, modeling, and processing methodology, design guidelines to achieve specific device characteristics are given.
A three-dimensional CMOS architecture is introduced and implemented. It is based on FinFET structure and is called Stacked Fin CMOS device. By stacking n-FET on top of p-FET, ~50% area reduction can be achieved over conventional two-dimensional cases. 3-D CMOS circuit cells, such as inverters and SRAM, have also been demonstrated. 3-D structure introduces another dimension to increase the circuit density in the CMOS platform. The vertical stacking of the MOSFET also reduces the interconnect-routing trace length, and therefore reduces the capacitive load on the driving circuits, resulting in lower power dissipation and higher performance. Based on this 3-D technology, we introduce a local-cluster interconnection methodology for 3-D ICs. These 3-D multi-gate devices, technologies, and circuits are very promising for ultra high density and high performance circuit applications.|
|Description: ||Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2005|
xvi, 160 leaves : ill. ; 30 cm
HKUST Call Number: Thesis ELEC 2005 WuX
|Appears in Collections:||ECE Doctoral Theses|
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