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| Title: | A low-dropout regulator for SoC with Q-reduction |
| Authors: | Lau, Sai Kit
Mok, Philip
Leung, Ka Nang |
| Keywords: | Low-dropout regulator
Power management
Q-reduction |
| Issue Date: | Mar-2007 |
| Citation: | IEEE journal of solid-state circuits, v. 42, no. 3, March 2007, p. 658-664 |
| Abstract: | A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 μA, is introduced in this paper. The idea has been implemented in a standard 0.35-μm CMOS technology (VTHN ≈ 0.55 V and |VTHP| ≈ 0.75 V). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without Q-reduction circuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current. |
| Rights: | © 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. |
| URI: | http://hdl.handle.net/1783.1/3049 |
| Appears in Collections: | ECE Journal/Magazine Articles
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