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|Title: ||A SPICE model for thin-film transistors fabricated on grain-enhanced polysilicon film|
|Authors: ||Jagar, Singh|
Cheng, C. F.
Poon, Vincent M. C.
Kok, C. W.
Integrated circuit modeling
Thin film transistors
|Issue Date: ||2002 |
|Citation: ||IEEE transactions on electron devices, v. 50, no. 4, April 2003, p. 1103-1108|
|Abstract: ||A simulation program with integrated circuit emphasis (SPICE)-compatible thin-film transistor (TFT) model for TFTs formed on grain-enhanced polysilicon (poly-Si) film by metal-induced-unilateral crystallization (MIUC) is presented. Due to the regularity of grain structures resulting from the MIUC process, the GBs are organized into a manhattan grid. The specific grain boundary (GB) organization allows a physics-based model to be developed. The model is based on the popular BSIM3 submicron CMOS model framework, which captures most of the physical effects in both long channel and short channel down to the submicron dimension. The model has been verified by a large amount of experimental data and shown to be applicable over a wide range of TFT processes with the application of grain-enhancement techniques such as solid-phase crystallization (SPC) and MIUC.|
|Rights: ||© 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.|
|Appears in Collections:||ECE Journal/Magazine Articles|
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