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Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/3237
Title: An analytical expression for drain saturation voltage of polycrystalline silicon thin-film transistors
Authors: Hao, Han
Wang, Mingxiang
Wong, Man
Keywords: Semiconductor device models
Silicon
Thin film transistors
Issue Date: 2008
Citation: IEEE electron device letters, v. 29, no. 4, April 2008, p. 357-359
Abstract: A physical-based analytical expression for the drain saturation voltage VDsat of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is derived. VDsat is found to be dominated by the grain boundary potential barrier modulation effect, which can be readily estimated from the device transfer characteristic. Straightforward prediction of VDsat values at arbitrarily given gate voltages based on the proposed formula is demonstrated for both low temperature and high temperature processed poly-Si TFTs in either n- or p-type. The prediction agrees well with experimentally determined VDsat value. Derivation of the expression is based on our previously proposed analytical ON-state drain-current model for poly-Si TFTs, with no empirical factors included.
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URI: http://hdl.handle.net/1783.1/3237
Appears in Collections:ECE Journal/Magazine Articles

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