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http://hdl.handle.net/1783.1/3272
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| Title: | Design of area-efficient, low-quiescent-current LDOs for chip-level power management |
| Authors: | Man, Tsz Yin
Mok, Philip
Chan, Mansun |
| Keywords: | Low-quiescent-current low-dropout regulators
Area-efficient design methodology
Power transistors |
| Issue Date: | 2007 |
| Citation: | Proceedings International Symposium on Integrated Circuits, 2007, ISIC '07, Singapore, 26-28 September 2007, p. 61-64 |
| Abstract: | In this paper, design methodology of area-efficient and low-quiescent-current low-dropout regulators (LDOs) for chip-level power management is proposed. As LDO chip size is dominated by the large size power transistor, guidelines are given to minimize its size when design specifications such as the dropout voltage, the minimum input voltage and the maximum load current are given. The reduced power transistor size also helps to maintain satisfactory error amplifier slew-rate at low quiescent current consumption. Stability of LDO designed under the proposed methodology is thoroughly studied. Extensive simulations are done to verify the stability study. |
| Rights: | © 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. |
| URI: | http://hdl.handle.net/1783.1/3272 |
| Appears in Collections: | ECE Conference Papers
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| 044417961.pdf | | 1670Kb | Adobe PDF | View/Open |
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