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Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/4324
Title: Low power low phase noise CMOS LC quadrature voltage-controlled oscillators
Authors: Chan, Tat Fu
Issue Date: 2007
Abstract: The demand for high-speed wireless data communication systems is continuously increasing such as 802.11a wireless local area network (WLAN). The development of high integration level and single chip solution for system is desirable to enable implementation at low cost and low power. The fully integrated transceivers of these systems are possible to implement in continuing advance’s complementary metal oxide semiconductor (CMOS) which have allowed low cost of transceiver design in the multi-gigahertz frequency range. Among the building blocks of frequency synthesizer, voltage-controlled oscillator (VCO) is an important block since it significantly affects the system performance of transceiver. Therefore, continuous researches have been motivated to focus on low-power, low phase-noise and high frequency’s fully integrated VCO implementations. In this thesis, two low-power high frequency CMOS LC quadrature voltage-controlled oscillators (QVCOs) have been designed and demonstrated. Both designs are fabricated in 0.13μm CMOS technology. The first one is a 0.8-V CMOS quadtrature LC VCO using capacitive coupling (CC-QVCO). By using capacitors as coupling elements, two LC VCOs are forced to oscillate in quadrature phase in a low power and low phase noise way. Fabricated in a 0.13um CMOS process and operated at 0.8-V supply, the proposed QVCO measures phase noise of -112dBc/Hz at 1M offset from 4.91GHz while drawing a total current of 4mA, which corresponds to a FOM of 181 dB. The core area is 0.278mm2. The Second design is a A 1-V CMOS quadrature LC VCO using diode coupling. By using diode’s reifying characteristic, second harmonic current component is generated the common source of cross-coupled pairs such that lock the two LC VCOs to operate in quadrature mode. At 1-V supply and at 3.9GHz, the QVCO measures phase noise of -117dBc/Hz at 1-MHz offset while dissipating 7.5mA which corresponds to a figure of merit of 180dBc. The core area is 0.37mm2.
Description: Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2007
xiv, 110 leaves : ill. ; 30 cm
HKUST Call Number: Thesis ECED 2007 ChanT
URI: http://hdl.handle.net/1783.1/4324
Appears in Collections:ECE Master Theses

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