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Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/4421
Title: Investigation of drain electric field and impact ionization in SOI MOSFETs
Authors: Ng, Chi Man
Issue Date: 1996
Abstract: Silicon-On-Insulator (SOI) CMOS technology is a potential candidate for the future main-stream technology in high-performance and lower-power logic applications. However, a device reliability problem, that comes with the early bipolar-induced breakdown, has to be solved before this potential is fulfilled. A novel "Quasi-SO1 (QSOI) MOSFET" structure can improve the device reliability by providing a channel-substrate overlap to sink the impact-ionization- generated carriers, while preserving the advantages SOI devices from the drain-side buried oxide. It also allows one to measure impact ionization current directly and use it as a compo-nent in a feedback model to predict the bipolar breakdown behaviour in SOI MOSFET. In this research, theoretical models for bulk MOSFETs were reviewed and modified in order to be suitable for modelling the maximum drain electric field in SOI MOSFET. Measurements and simulations confirmed a reduced substrate current as evidence of reduced maximum drain electric field in a QSOI MOSFET. This implies a smaller parasitic bipolar component, thus enhanced device reliability in true SOI MOSFETs. Moreover, device scaling effects on the maximum drain electric field were investigated by performing simulations on SO1 MOSFET structures with different structural parameters. An empirical model of characteristic length, which is a modified version of the El-Mansy/Ko model, was obtained for SO1 MOSFETs. In addition, despite the importance of the energy-dependent model over the local-field model in submicron devices, particularly in impact ionization prediction, it was found that the El-Mansy/ Ko model can still be applied with appropriate modifications of the homogeneous ioni-zation coefficients. This is important because it allows simple empirical calculations to provide physical insights for device design. The implications on device scaling and drain engineering are also discussed.
Description: Thesis (M.Phil.)--Hong Kong University of Science and Technology, 1996
ii, 109 leaves : ill. ; 30 cm
HKUST Call Number: Thesis ELEC 1996 Ng
URI: http://hdl.handle.net/1783.1/4421
Appears in Collections:ECE Master Theses

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