HKUST Institutional Repository >
Electronic and Computer Engineering >
ECE Master Theses >
Please use this identifier to cite or link to this item:
|Title: ||A 70 MHz CMOS band-pass sigma-delta analog-to-digital converter for wireless receivers|
|Authors: ||Hsu, Issac Kuan Chun|
|Issue Date: ||1999 |
|Abstract: ||Analog-to-digital converters play an essential role in modem RF receiver design. Conventional Nyquist converters require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can be implemented using simple and high-tolerance analog components. Moreover, sampling at high frequency eliminates the need for abrupt cutoffs in the analog anti-aliasing filters. A technique of noise shaping is used in σδ converters in addition to oversampling to achieve a high-resolution conversion. A significant advantage of the method is that analog signals are converted using simple and high-tolerance analog circuits, usually a 1-bit comparator, and analog signal processing circuits having a precision that is usually much less than the resolution of the overall converter.
In this thesis, a technique to design the σδ converters for 70 MHz will be described. Impulse-invariant-transformation is used to transform a discrete-time (z-domain) loop-filter transfer function into continuous-time (s-domain). The continuous-time loop-filter is then implemented using a transconductor-capacitor filter. A latched-type comparator and a TSPC D Flip-flop are being used as the quantizer of the σδ converter. Two second-order band-pass σδ converters have been implemented in a MOSIS HP 0.8μm CMOS technology and a MOSIS HP 0.5μm CMOS technology respectively.
For the first converter, at supply voltage of 3 V, the maximum signal-to-noise-and-distortion-ratio (SNDR) is measured to be 35.14 dB, which corresponds to a resolution of 5.9 bits, at an input voltage being 0.17 V. The total current supply at 70 MHz is around 10 mA. For the second converter, at both supply voltages of 2.5 V and 3 V, the maximum SNDR is measured to be 42.0 dB, which corresponds to a resolution of 7 bits, at an input voltage being around 0.2V. The total current supply at 70 MHz is 15.5 mA.|
|Description: ||Thesis (M.Phil.)--Hong Kong University of Science and Technology, 1999|
x, 88 leaves : ill. ; 30 cm
HKUST Call Number: Thesis ELEC 1999 Hsu
|Appears in Collections:||ECE Master Theses|
Files in This Item:
All items in this Repository are protected by copyright, with all rights reserved.