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Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/4648
Title: Routing and time-slot assignment in photonic circuit switching networks
Authors: Yu, Wing Wa
Issue Date: 2002
Abstract: Going beyond wavelength switching, researchers have proposed several packet-based optical switching schemes. These schemes allow the bandwidth of an individual wavelength channel to be further sub-divided in a dynamic way, as optical network users may not always require the full capacity of a wavelength channel. These packet-based optical switching schemes include Optical Burst Switching (OBS) and Optical Packet Switching (OPS). One of the challenges of the OBS and OPS schemes is the implementation of the optical buffer. The only optical technology that appears feasible for providing optical buffer in the near future is Fiber Delay Line (FDL). Compared with Random Access Memory (RAM) electronic buffer, FDL is basically a first-in-first-out fixed delay line. Implementation of optical buffer by FDL is complicated and relatively expensive. We believe that optical buffering must be used sparingly and effectively in optical networks. The second challenge of the OBS and OPS schemes is the complexity in header processing. We introduce the concept of Photonic Circuit Switching (PCS) as a method for sub-division of the capacity of a wavelength channel in optical networks. The advantage of PCS is that header processing is not required, and that with proper designs, optical buffer requirement can also be minimized. PCS is completely analogous to TDM circuit switching, except that it operates in the optical domain while the latter operates in the electronic domain. Hence, in PCS, signal transmission on a link is partitioned into fix-sized time-slots and these time slots are organized into repetitive frames of a fixed number of slots. The focus in this thesis is to consider ways to route and select time slots for photonic circuits so that buffering requirement in the network can be minimized. We refer to this as the Time-slot Assignment (RTA) problem. Some heuristic algorithms for RTA are investigated, and comparisons are made between coupled schemes and uncoupled schemes - in the former routing and time-slot assignment are solved together as one problem, and in the latter the routing problem is solved first. A shortest path algorithm is devised such that by expanding the network into a set of virtual nodes, we can flexibly solve the RTA problem under various bandwidth/buffer cost. In our quantitative results, measurements of bandwidth blocking and buffer blocking probabilities are presented which should serve as an important guidance to designers of PCS networks.
Description: Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2002
xi, 70 leaves : ill. ; 30 cm
HKUST Call Number: Thesis ELEC 2002 YuW
URI: http://hdl.handle.net/1783.1/4648
Appears in Collections:ECE Master Theses

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