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|Title: ||A nano-scale double-gate flash memory|
|Authors: ||Yuen, Kam Hung|
|Issue Date: ||2003 |
|Abstract: ||With the growth of the multi-media applications in portable electronic products, the demand of ultra-high density nonvolatile memory is enormous. Multi-bit cell, in addition to device scaling, is a promising approach to increase the memory density. However, the scaling of floating gate nonvolatile memory is a challenge. Due to the data retention, the minimum thickness of the tunneling oxide and the blocking oxide are about 9nm and 15nm . Without the vertical scaling, horizontal shrinkage introduces short channel effect. In this work, a flash memory device using asymmetric double gate (ADG) MOSFET is proposed. Combining 2 storage nodes at the front and back gate oxide together with the localized charge trapping in the source and drain side, the ADG nonvolatile memory (NVM) can store at most 4 bits per cell. Channel hot electron (CHE) injection and Fowler-Nordheim (FN) tunneling are used for program and erase respectively. As the DG MOSFET is the most promising candidate for scaling in the deep nanometer regime, NVM with similar structure can potentially be a nano-scale flash memory device.
A 4 bits asymmetric double gate flash memory cell and a 2-bit ADG flash architectures are introduced in this research project. The 4-bit ADG NVM increases the storage capacity of the memory through the use of multi-bit storage. The 2-bit ADG NVM shows the superior scalability. The operation principles, including programming, erasing and reading, of the ADG NVM are demonstrated by 2-D device simulation with MEDICI. A NOR array structure of the proposed novel NVM cell are also studied and described in this work.|
|Description: ||Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2003|
xvii, 77 leaves : ill. ; 30 cm
HKUST Call Number: Thesis ELEC 2003 Yuen
|Appears in Collections:||ECE Master Theses|
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