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|Title: ||Technology, characteristics, and modeling of large-grain polysilicon MOSFET|
|Authors: ||Singh, Jagar|
|Issue Date: ||2002 |
|Abstract: ||A large grain size and a high material quality of polysilicon (p-Si) film is desirable for high performance thin-film transistors (TFTs), which have the potential to be used in applications such as 3-D circuits and AMLCDs. A method to form a large-grain p-Si on an insulator (LPSOI) film with a grain size in the order of tens of microns and with very high material quality is proposed and it includes the metal induced lateral crystallization (MILC) of a-Si, followed by a high temperature annealing (900°C) process.
The n-channel LPSOI MOSFET demonstrates a very high μ (450cm2/ V.s), low Vt (0.1V), a steep S (70mV/dec), and low Ioff (1x10)8 at Leff= 0.5 μm. The fT of p-channel MOSFETs can reach up to 5.3 GHz at Leff= 0.7 μm. The orientation control of grain boundaries (GBs) due to the MILC process leads to better device performance, but that performance varies with different orientations. With scaling, such effects significantly decrease, however, Ioff increases, which causes device failure, especially at large W. To design wide and short devices, the cause of Ioff as well as other device design related parameters, such as the device distance from the crystallization window and source/drain reversal, are examined. This leads to new layout strategies at different W and L, for example a ladder-like device layout, which significantly improves the performance and scaling properties. The effects of small geometries are also studied. Finally, a TFT model that is based upon Poisson distribution and BSIM is proposed, and it has the capability of predicting device behavior with statistical variations.|
|Description: ||Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2002|
xviii, 134 leaves : ill. ; 30 cm
HKUST Call Number: Thesis ELEC 2002 Singh
|Appears in Collections:||ECE Doctoral Theses|
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