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Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/6958
Title: Low power pipelined ADC with non-linear calibration
Authors: Fung, Sheung Wai
Issue Date: 2010
Abstract: Pipelined analog-to-digital converter (ADC) design is popular for high speed data conversion (10-100 MS/s) with medium-to-high resolution (8-14bits). Moreover, low power pipelined ADC is important for portable and handheld wireless devices. Capacitor mismatch and finite operational amplifier (OPAMP) gain induce linear and non-linear errors and limit the performance of pipelined ADC. Thus, a large sampling capacitor size and high-gain OPAMP should be implemented in a conventional pipelined ADC in order to minimize those errors. Consequently, high power is consumed for a conventional pipelined ADC. In this thesis, a non-linear interpolation-based calibration architecture is introduced. The digital calibration procedure can compensate both linear and non-linear errors so that the capacitance size can be reduced and the OPAMP gain can be lower. As a result the pipelined ADC analog power can be dramatically reduced. The architecture includes a low power raw pipelined ADC and a high resolution algorithmic ADC. The algorithmic ADC aims to measure the non-linear error of the raw pipelined ADC and compensate it by interpolation-based procedure in the digital domain. As a result, the OPAMP in each multiplying digital-to-analog converter (MDAC) can be designed with a low-gain and simple structure and the size of sampling capacitor can be smaller. Therefore, the total power consumption of the pipelined ADC can be greatly reduced. Although the cost of the calibration circuit is increased in the digital domain, the digital processing area and power will dramatically decrease due to the trend of CMOS scaling. Thus the power saving in the pipelined ADC should surpass the power consumption of the calibration part. The architecture is implemented in a 12-bit 20-Msamples/s pipelined ADC in AMS 0.35μm CMOS technology with differential input voltage ranged from −1V to +1V and the supply voltage is 3.3V. The pipelined ADC achieves 41.3dB and 72.5dB SNDR before and after calibration with an input frequency of 595.7 kHz. The SNR of the pipelined ADC is 72.77dB and the FOM is 0.78pJ/step. The analog power consumption of the whole pipelined ADC and calibration circuit is 55.74mW, and the chip area is 4.83×4.32 mm2.
Description: Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2010
xviii, 112 p. : ill. ; 30 cm
HKUST Call Number: Thesis ECED 2010 Fung
URI: http://hdl.handle.net/1783.1/6958
Appears in Collections:ECE Master Theses

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