Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/2410

Low-loss on-chip interconnects for silicon integrated radio-frequency and microwave systems

Authors Leung, Lydia Lap Wai
Issue Date 2005
Summary With the rapid development in wireless and portable communication, there is an increasing demand for low-cost and miniaturized radio-frequency (RF) and microwave monolithic integrated circuits. While the active transistors have experienced steady enhancement in device performance as a result of the advancing CMOS technology, it is still challenging to realize low-loss high-frequency interconnects on standard CMOS-grade silicon substrates, which normally have low-resistivity in the range of 1 - 20 Ω-cm. In this thesis, we study the lossy mechanisms, which are dominated by substrate loss and metallic loss, of interconnects on standard CMOS-grade silicon substrates. Our goals are to design, fabricate, characterize and model high-performance interconnects on lossy substrates. Three different kinds of processing technologies are proposed: interconnects employing high-conductive copper on low-loss low-k dielectric material - BCB, micromachined edge-suspended coplanar waveguides and high-aspect ratio through-wafer interconnects vias. Thick copper-electroplated thin-film passive components including microstrip line, low-pass filter and coplanar waveguides were designed and fabricated on standard CMOS-grade silicon employing a thick low-loss low-k dielectric interfacing layer to reduce both the substrate loss and the metallic loss. We also propose the use of the micromachining process to remove the substrate along the edge of the interconnects, where the coupling is the strongest to achieve the edge-suspended structures, which reduce signal coupling to the lossy silicon substrate at radio frequency and provide support mechanical support simultaneously. Measurement and EM simulation results reveal the working mechanisms and performance of the proposed processing technologies. The technologies can be generally applied to achieve low-cost and high-performance on-chip passive components on standard CMOS substrate. Moreover, the fabricated edge-suspended coplanar waveguides have been characterized and a compact equivalent circuit model has been derived over a broad frequency range. The circuit is further extend to the modeling of crosstalk between the finite ground suspended CPWs. For the realization of high-density, reliable, low-parasitic and low-cost packaging and novel three-dimensional electromagnetic structures on silicon substrate, high-aspect ratio through-wafer vias are needed. With the use of the state-of-the-art micromachining technology and the bottom-up electroplating approach, high-aspect ratio through-wafer vias on thick silicon substrate with dimensions ranging from 50 μm to 70 μm have been achieved, characterized and modeled.
Note Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2005
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Language English
Format Thesis
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