||With the increasing market of RF/Microwave product, compact, low power and high performance system integration solutions are needed. Research has been focused on System-On-Chip (SOC) technology and System-On-Package technology. SOC technology can provide high efficiency integration with digital and analog blocks. But the performance of passive components in SOC is not satisfactory. SOP technology can provide high performance passive components using packaging technique while active devices are realized in available technologies. Meanwhile, accurate and fast passive device model is needed for system integration and optimization purpose. High-Q Cu inductors using low-K Benzocyclobutene (BCB) dielectric are fabricated on standard CMOS silicon substrate as a SOC approach. Metal ohmic loss and substrate loss, the two major factors that degrade the Q-factors of on-chip inductors, are reduced by the employment of electroplated copper and the BCB dielectric, respectively. The inductor fabrication process is low-cost and low-temperature, making it suitable for post-IC process for high-performance RFIC's and MMIC's. In our SOP approach, high Q copper inductors are fabricated on low-cost and low-loss BT and glass substrate using electroplating process. A differential LC VCO circuit was designed using these high Q inductors at 2.4GHz. Flip chip technology is applied to assemble the active chips on BT and glass substrate. This technique can be extended to other building blocks thus realize integration of the whole RF system. A physical based analytical model for on-chip inductors is developed. Ladder structure is used to model the skin and proximity effect in the metal lines. Substrate electric and magnetic loss is accurately modeled using RC and simple RL ladder structure respectively. All the model parameters can be calculated from the layout and process parameters. This generic model can be applied to various substrate resistivities, thus suitable for different technologies.