Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/3140

A SPICE model for thin-film transistors fabricated on grain-enhanced polysilicon film

Authors Jagar, S
Cheng, CF
Zhang, SD
Wang, HM
Poon, MC
Kok, CW
Chan, MS
Issue Date 2003
Source IEEE transactions on electron devices , v. 50, (4), 2003, APR, p. 1103-1108
Summary A simulation program with integrated circuit emphasis (SPICE)-compatible thin-film transistor (TFT) model for TFTs formed on grain-enhanced polysilicon (poly-Si) film by metal-induced-unilateral crystallization (MIUC) is presented. Due to the regularity of grain structures resulting from the MIUC process, the GBs are organized into a manhattan grid. The specific grain boundary (GB) organization allows a physics-based model to be developed. The model is based on the popular BSIM3 submicron CMOS model framework, which captures most of the physical effects in both long channel and short channel down to the submicron dimension., The model has been verified by a large amount of experimental data and shown to be applicable over a wide range of TFT processes with the application of grain-enhancement techniques such as solid-phase crystallization (SPC) and MIUC.
Subjects
GBs
ISSN 0018-9383
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Language English
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