||While CMOS continues to be the technology of choice to enable a low-cost Radio Frequency Identification (RFID) integrated circuit solution, embedding the nonvolatile memory (NVM) in the RFID chip is a major barrier to achieving the 5-cent tag cost target. Existing NVMs such as the FLASH, aside from having technology scaling limitations, require additional masks and process modifications to CMOS that tend to increase the overall cost. Other types of NVMs such as the antifuses (AF) do not have scaling limitations and are cheaper to fabricate than FLASH, but the mainstream AFs still require three masks to the standard CMOS. Meanwhile, in forming the memory cell and the programming circuit, the inherent use of high voltages in programming the NVMs may require the use of high-voltage tolerant devices that are not part of the standard process flow. The thesis addresses these challenges and presents antifuse structures, memory cell and array configuration, as well as high-voltage-tolerant programming circuits that can be readily integrated in conventional CMOS. In Chapter 2, antifuse structures requiring no additional masks to CMOS are discussed. MOS transistor-based and polysilicon diode antifuses are described and the measurement results of the fabricated devices are presented. Based on the characteristic of the devices, their feasibility as RFID memory elements are evaluated. Chapter 3 describes feasible memory cell configurations that consider the cell size and the high-voltage reliability concerns. The cell uses a 1-transistor with antifuse configuration with HV switch circuits to circumvent issues on high voltage stress. In Chapter 4, high-voltage tolerant switch solutions that are composed of conventional CMOS devices are described. The circuit designs do not consume DC current during programming unlike conventional solutions. One of the proposed HV switch circuit is fabricated and is integrated in a memory array to validate the array and circuit functionality. Furthermore, a prototype memory array was fabricated that validates the feasibility of the device, the memory cell and the circuit in a 0.18 μm CMOS technology. Finally, in Chapter 5 the thesis draws the conclusions on the study of nonvolatile memories for RFID applications.