||Driven by the demand for lower cost, lower power, and higher data rates in both wireless and wired communication system, integrated circuits and systems are constantly pushed toward higher operating frequency and lower power consumption. Furthermore, attributed to the continuous device scaling and the need to reduce the power consumption of the digital circuits implemented in CMOS process, the supply voltage for analog and RF systems has to be lower. Voltage-controlled oscillator (VCO), as an integral part of fully-integrated phase-locked loop for clock generation, should be capable to operate at high frequency from a low supply voltage with low power consumption. In this thesis, two low-voltage high-frequency voltage-controlled oscillators have been designed and demonstrated. The first one is a 1-V 17GHz 5mW CMOS quadrature voltage-controlled oscillator (QVCO) based on transformer coupling. By using a transformer as the coupling element to couple two LC oscillators to oscillate in quadrature, high-frequency, wide-tuning-range and low-phase-noise performance are achieved. Implemented in a 0.18-μm CMOS, the QVCO achieves a tuning range of 16.5% at 17GHz, and phase noise of -110dBc/Hz at 1MHz offset, for a current consumption of 5mA from a 1V supply. The QVCO occupies an area of 0.37mm2 with a FoM of 187.6dB. The second design is a 1-V 24-GHz 17.5mW fully-integrated phase-locked loop (PLL), which employs a transformer-feedback voltage-controlled oscillator (TF-VCO) and a stacked divide-by-2 frequency divider for low voltage and low power. Implemented in a 0.18-μm CMOS and operated at 24 GHz with a 1-V supply, the PLL measures an in-band phase noise of -106.3dBc at a frequency offset of 100kHz and a out-band phase noise of -119.1dBc/Hz at a frequency offset of 10MHz. The PLL dissipates 17.5mW and occupies a core area of 0.55 mm2.