||Radio Frequency Identification (RFID) has attracted worldwide attention in recent years. Different protocols of RFID system have been developed for different applications varying from stored-value travel card to good tracking application in logistic industry. One of the protocols, the EPCglobal Class-1 Generation-2 UHF RFID, is of global interest recently because of its multi-regulatory supportive features and the dense-reader operating environment. While most are putting efforts in research and development of advanced tag design, there are still many aspects in reader design, such as system size and power reduction, which have not been explored yet. Currently most reader solutions are discrete-components type of big size and high power consumption. Single-chip reader solution becomes a hot candidate to replace the old one. In this thesis, a design of digital signal processing portion for a single-chip reader transceiver is proposed. This single-chip design targets at the EPCglobal Class-2 Generation-2 protocol. Interference by other readers to the Tag-to-Reader link is a severe problem in the dense-reader operating environment for this protocol. A mixed-signal channel select filtering receiver architecture with an oversamped A/D converter is employed to handle this problem. The oversampled A/D converter is a delta-sigma modulator which requires a decimation filter in digital domain to process its output before further processing. Beside the decimation filter in receiver, descriptions of the rest of digital part are also given. The digital part has been integrated with its analog counterpart on ASIC using TSMC 0.18μm standard CMOS process. FPGA prototyping of digital part has also been done. The implementation procedure involving a few EDA tools, testing of chips, and FPGA prototyping are presented. Potential issues of the design and improvements are discussed as well.