Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/4342

Low power VLSI baseband system design for EPC C1G2 radio frequency identification (RFID) applications

Authors Man, Sau Wing
Issue Date 2007
Summary RFID is an automatic identification technology which can be applied in many applications, such as supply chains management, product tracing, building access control and automatic product checkout. The cost of a passive RFID tag has been dropped to the range between 0.05 and 0.1 USD, and this stimulates the growth of its usage. With RFID technology, fast and accurate recognition of objects could be achieved with a very low cost. At the same time, the mass usage of RFID has raised concerns regarding security and privacy issues. One of the primary security concerns regarding RFID technology is the illicit tracking of RFID tags. For examples, thieves with RFID readers could scan and track crowds for high-value banknotes. Police could also abuse a convenient method of cradle-to-grave surveillance. The existing passive tag is small and highly mobile, and there is no agreed security solution for low cost RFID systems in the market. Therefore, a passive tag is easily trailed, monitored and even copied by adversaries. Conventionally the simplest way to enhance privacy is to directly “kill” the tag after purchase, but the drawback is that the clients could not use the tag anymore. Another approach is to use hash-lock schemes to authenticate the readers. However, this method does not eliminate the threat of passive eavesdropping. If an adversary hears commands during the authentication communication between the reader and the tag, he would access the sensitive information. This thesis describes a low power implementation of a secure EPC UHF Passive RFID Tag baseband system and an AGC circuit. In the tag side, to ensure secure information transaction of the tag, traditionally the focus is on directly applying a low-complexity encryption engine. However, this approach could lead to the problem of known-plaintext attack (KPA). The attacker could make use of the known header to reveal the secret key. Our contributions consist of proposing a novel dataflow solution enforced by an AES cryptography engine embedded inside the passive RFID tag. Also, various low power design techniques are proposed to reduce the power consumption of the baseband of the passive tag. In particular, we propose a moving window PIE decoding algorithm and an improved Tausworthe sequence generator to reduce the power consumption. Other low power design techniques such as clock gating, optimal clock driving and parallel operations are extensively used in the design of the tag. The complete RFID tag, which consists of an analog frontend, 136 bits one-time programmable (OTP) memory, charge pump, rectifier, clock divider, and the proposed baseband system, was designed using TSMC 0.18μm process and was verified. In the Reader side, an effective automatic gain controller is implemented for the Reader. It takes the average of the estimated power from the received signal in real time and controls the gains in LNA, AAF and CSF by a feedback loop. The theory for automatic controlling is proposed by Peter Alriksson in high speed WCDMA terminals, and we adopt it in our proposed Automatic Gain controller architecture. Our main contributions in the reader part are on the adaptation and implementation part. The AGC system has been implemented and verified by Xilinx Virtex-II Prototype platform with FPGA XC2V1500.
Note Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2007
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Language English
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