||Silicon-On-Insulator (SOI) CMOS has many potential advantages over the traditional bulk CMOS circuits as it is free of latch-up and has improved performance and higher packing density. With recent advances in high-quality thin-film SOI wafer technology, SO1 CMOS technology will become a viable technology for ULSI. As SOI emerges as an alternative to bulk CMOS for low power and high-speed applications, an automated methodology will expedite the conversion of existing bulk CMOS designs to SOI CMOS. Without the n-well(or p-well), substrate contacts and well contacts, we should be able to reduce the size of SOI design by eliminating these unnecessary area. We will present a methodology for converting bulk CMOS polygon layout to SOI so that we could obtain a smaller converted cell. During conversion, the transistors of the original bulk layout will be replaced by parameterized cells. Then, the interconnection wires will be converted to symbolic wires. By counting well area, we will get smaller SOI cells than the original layout. In addition, test structures for both SOI and bulk technology are designed. The SOI circuits performance are characterized and compared using inverter, 2-inputs NAND, 3-inputs NAND and 4-inputs NAND ring oscillators. The digital circuits of different types of devices can then be compared. Inverter chains are used for the characterization of the floating-body effect in SOI circuits. Single devices are also included for parameters extraction.