||Recently, Silicon-On-Insulator (SOI) technology has been actively promoted as a potential candidate for next generation of ultra-large integrated circuits. The advantages include latchup immunity, higher current drive capability, smaller parasitic capacitance and simpler processing steps. Some circuits such as SRAMs and OTAs have already been realized in SOI. Although the DC I-V characteristics of SOI MOSFET has been studied extensively down to deep submicron regime, there are stiIl no complete compact model for the S/D junction capacitance in SOI. A new junction capacitance model for SOI devices has been developed for circuit simulation. In SOI technology, its small parasitic capacitance is primarily attributed by : (1) the reduced bottom-wail S/D-to-substrate capacitance due to underneath buried oxide; and (2) the single-sided S/D side-wall capacitance in SO1 rather than four-sided in bulk because of the mesa isolation in SOI. Based on this intrinsic advantage, a narrow-width methodology (NWM) suitable for analog gain stage design in SOI technology is presented in this thesis. By employing NWM, we can achieve better circuit performance in SOI when compared with bulk CMOS. Given the same testing conditions for both bulk and SOI 2-stage Miller compensated op amp, our study showed a better speed performance and a smaller compensation capacitance required for ensuring stability in SOI. With a judicious choice of transistor sizes, the speed advantages of SOI circuits over bulk in folded-cascade op amp topology is also exploited.