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Low power VLSI architectures for video applications

Authors Lam, Kin Hung
Issue Date 2001
Summary Portable devices with multimedia capability, such as mobile videophones and personal digital assistants (PDA), are becoming an integral part of our daily life. Such devices are usually powered by batteries that have limited amount of energy and hence low power consumption becomes one of the most critical design criteria for these devices. Real time processing of multimedia data, especially video sequences, with traditional algorithms and architectures requires high performance systems that consume a lot of power. This contradicts with the low power consumption requirement of portable devices. In this thesis, low power VLSI architectures, which exploit both algorithmic and architectural low power design techniques, for the motion estimation module in a video encoder are presented. An algorithm selection scheme reducing the number of computations in run-time is proposed to reduce power consumption in the algorithmic level. A 2-D processing element array reducing power consumption through switching activity reduction in architecture level using the notion of suspendable processing is also discussed. An architecture with an efficient data flow implementing the latest diamond-search-pattern-based motion estimation algorithms, such as Advanced Diamond Zone Search, is proposed to reduce the power consumption by minimizing the number of costly memory accesses.
Note Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2001
Language English
Format Thesis
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