Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/4584

System level power optimization and estimation

Authors Zou, Peiqing
Issue Date 2001
Summary Higher integration density, smaller device geometry, larger chip size, faster clock frequency, and the demand low power consumption have made power related issues increasingly critical in VLSI circuits. A new generation of power-conscious CAD tools are coming into the market to help designers estimate, optimize and verify power consumption levels at most stages of the IC design process. Circuit and system designers need tools that allow them to explicitly control the power budget during the early phases of the design process. This is because the power savings obtainable through automatic optimization early in the design process is usually more significant than the achievable by means of lower level optimization. In this thesis work, we develop an approach to generate finite state machine specification in such a manner that decomposition technique can achieve more power savings when it is applied to the new specification. Pattern extraction and constrained allocation to the data path are used when generating the controller finite state machine. An estimation scheme has been developed to estimate the power consumption for a C program to be run on a processor. Data flow transformation, module binding and scheduling are used to carry out the results. This scheme estimates the latency as well as the energy consumption of the program. A module library has been built to help the estimation.
Note Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2001
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Language English
Format Thesis
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