||Synchronous circuit is currently the most popular implementation method for digital circuit. However, its performance is limited by the worst-case delay of the slowest pipeline stage. At the same time it also suffers from clock skew problem and heavy loading of the global clock signal. Asynchronous circuit design has been proposed long ago for solving the above problems and it has intrinsic advantages over synchronous circuit design. Some of the advantages are average-case delay performance instead of worst-case delay, low power dissipation in idle mode, low voltage noise, low electromagnetic emission and clock skew free. Also it is flexible to remove or insert a pipeline stage. However, the asynchronous circuit design suffers from large local handshaking overhead, which limits its deployment for real life circuit. In this thesis, we investigate on the methods that reduce the overhead of the asynchronous circuit design in both pipeline operation scheduling and circuit level. In particular the theoretical optimal pipeline operation schedule was introduced and the improved design of the local stage controller, the completion detection circuit and the asynchronous pipeline were proposed to reduce the local handshaking overhead. Finally, an asynchronous pipelined butterfly unit for FFT operation has been designed and compared with the synchronous counterpart and other asynchronous circuit design styles to demonstrate the effectiveness of the proposed method.