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Buffer and scheduler design in high-speed switching fabric

Authors Cao, Qi
Issue Date 2005
Summary Memory used in high-speed switching often needs to be customer designed and is expensive. As the link speed approaches 10-Gbps and 40-Gbps rates, reducing memory requirement can translate into significant cost saving. In this thesis we study optimal memory partition scheme between ingress ports and egress ports of a crossbar-based switch. We show in this thesis how the optimal partition between ingress and egress ports can save the memory, and how the partition is affected by the queue structure in the switch. Compared with the commonly used 50-50 partition, the optimal partition scheme can reduce buffer requirement by at least 30%. We also study another important practical issue which is the scalable scheduling algorithm problem in the multi-stage switch. The large switch is always made up from smaller ones where a multi-stage switch is formed. The conventional scheduling algorithm is too complicated to apply to the multi-stage switch since the information flow in terms of iteration times and request size between different stages are too large. We proposed a simple but effective algorithm which can reduce the information flow by using memory strategy.
Note Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2005
Language English
Format Thesis
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