||In recent RF front-end IC designs, CMOS technology has gained much more popularity for its low cost and feasibility of single-chip solutions. The applicability of scale-down CMOS technology further improves the performance which is comparable to the designs using BiCMOS, GaAs and SiGe. Power amplifier, the most power-hungry building block in the RF transmitter front-end, is always designed so that high efficiency is achieved to save power. In addition, recent trend has placed more focus on low-voltage, low-power design. Since the power amplifier is essential in terms of power consumption and efficiency that will degrade when decreasing the supply voltage, an optimized Power-Added-Efficiency (PAE) should be achieved under low voltage. In this thesis, the design considerations of a RF CMOS power amplifier under low supply voltage are detailed. A two-stage power amplifier operating at 2.4GHz under a 1-V supply voltage has been designed and fabricated for Bluetooth applications in a standard 0.18-μm CMOS technology. Different from existing methods, an on-chip transformer Q-enhancement circuitry is designed and utilized in the pre-amplifier design. This kind of topology effectively enhances Q of on-chip inductor as well as keeping its inductance value unchanged. For the second stage, the topology is an injection-mode locking which effectively relaxes the pre-amplifier driving problem. At the measurement stage, with the input power of -6dBm, an output power of 15.6dBm is achieved under a 1-V supply voltage with PAE 39.5%. The output power could go as high as 20.3dBm under a 1.8-V supply voltage with PAE 43%, which could be used for Class 1 Bluetooth applications. When applying a Bluetooth-modulated signal to the input of the PA, the measured output spectrum is well under the Bluetooth mask.