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Design and fabrication of a flip-chip-on-chip multi-chip module with 3D packaging structure and through-silicon-via for underfill dispensing

Authors Tsui, Yat Kit
Issue Date 2004
Summary An innovative package design for flip chip multi-chip modules (FC-MCM) was introduced in this research. The developed package has a flip-chip-on-chip structure. Four fiip chips (demonstration of DRAM) are assembled on a silicon chip carrier with eutectic Lead-Tin solder joints. The 100 μm solder bumps of flip chips are fanned-in on the silicon chip carrier to form an area array with 500 μm solder bumps. An optional through-silicon-via hole is made at the center of the chip carrier for underfill dispensing, if required. The whole multi-chip module is mounted on the printed circuit board (PCB) by the standard surface mount reflow process. After the board level assembly, all specimens are inspected by X-ray and divided into two groups. One group is encapsulated with underfill and the other group is not. For those packages with encapsulation, the underfill is dispensed through the aforementioned via hole to encapsulate the solder joints and memory chips. Subsequently, scanning acoustic microscopy is performed to inspect the quality of the underfill. Afterwards, all specimens are subjected to reliability testing. The accelerated temperature cycling (ATC) test and drop test are conducted. During the testing, the electrical resistance of the packages is monitored. The experimental results of ATC show that those packages without underfill encapsulation may fail in less than 100 thermal cycles and about 50% of packages with underfill can last for about 2,500 thermal cycles. From the records of real time resistance monitoring system, it is identified that the daisy chains are broken at extreme temperatures. From the dye ink analysis and the cross-section inspection, those packages without underfill have cracks inside the silicon chip carrier, right behind the pads of large solder balls. Similarly, those packages with underfill are also found to have cracks formed inside the silicon chip carrier under the cross-section inspection. From the results of acoustic microscope, defects are found in the underfill encapsulant at the corners of the packages after ATC testing. And it was identified by the cross-section. In the drop test, for the packages without underfill encapsulation, it was found that the silicon chips are broken into pieces even though the center part of them still attaches on the PCB by the large solder bumps. For the electrical monitoring system, an external circuit with a ten ohm resistor is applied for checking the daisy chain status. By measuring the voltage change of the resistor, the status of those daisy chains in the packages can be identified. From the results, it shows that the voltage of the resistor drop to zero while the silicon chip carrier is broken into pieces after dropping. From the dye ink analysis, it shows that a crack has been found under the solder bumps although it cannot be seen in the cross-section inspection. By SEM inspection and EDX analysis, it is found out that the failure is between the silicon oxide layer and the aluminum layer. In contrast, the packages with underfill still survived after 10 drops (5 drops in the Y-positive direction and 5 drops in the Y-negative direction). From the cross-section inspection, it is identified that the packages still have good solder joints after testing. The experimental results indicate that the underfill encapsulation is necessary for the present FC-MCM package structure in order to enhance the board level reliability. However, the reinforcement is mainly to prevent die cracking, instead of protecting the solder joints. Nevertheless, the present package design still has many advantages such as low profile, high capacity, and void-free encapsulation. With the reinforcement of underfill, it is believed that the present package design will have very good board level reliability.
Note Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2004
Language English
Format Thesis
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