Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/5286

3D packaging of multi-stacked flip chips with plugged through silicon vias for vertical interconnection

Authors Hon, Chi Kwong
Issue Date 2006
Summary Three-dimensional packaging (3DP) is an emerging trend in microelectronics development toward system in package (SiP). 3D flip chip stacking structures with through silicon vias (TSVs) have very good potential for the implementation of 3D packaging. The focus of the first part will be the fabrication of the through silicon vias (TSVs). Because the definition of the microvias is defined as a hole diameter of less than or equal to 150 μm according to IPC-6016, attention will be paid to laser drilling and deep reactive ion etching since these two methods can make the microvias, but wet etching cannot. Comparison between these two different methods is carried out in terms of wall straightness, smoothness, smallest via produced and time needed for fabrication. Wafer thinning is used to fabricate thinner through silicon microvias. The other part of the study is a prototype design and fabrication of multi-stacked flip chip three dimensional packaging (3DP) with TSVs for interconnection. Three chips are stacked together to make a 3DP with solder bumped flip chips. TSVs are fabricated and distributed along the periphery of the middle chip. The TSVs are formed by DRIE with dimensions of 150 x 100 microns. The TSVs are plugged by conductive adhesive or copper plating. The filled TSVs are connected to the solder pads by extended pad patterns surrounding the top and the bottom of TSVs on both sides of the wafer for the middle chip. After pad patterning passivation and solder bumping, the wafer is sawed into chips for subsequent 3D stacked die assembly. Because the TSVs are located at the periphery of the middle chips and stretch across the saw street between adjacent chips, they will be sawed through their center to form two open TSVs (with half of the original size) for electrical interconnection between the front side and the back side of the middle chip. The top chip is made by the conventional solder bumped flip chip processes and the bottom chip is a carrier with some routing patterns. The three middle chips and top chip are stacked by a flip chip bonder and the solder balls are reflowed to form the 3DP structure. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented in this thesis.
Note Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2006
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Language English
Format Thesis
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