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Design and Fabrication of a Silicon Interposer With TSVs in Cavities for Three-Dimensional IC Packaging

Authors Zhang, Rong HKUST affiliated (currently or previously)
Lo, Chi Chuen HKUST affiliated (currently or previously)
Lee, Ricky Shi-wei View this author's profile
Issue Date 2012
Source IEEE Transactions on Device and Materials Reliability , v. 12, (2), June 2012, p. 189-193
Summary Flip chip is one of the packaging techniques for high-performance components. There is a greater demand on integrating more functions in a smaller chip nowadays. This leads to the increase of I/O density. Organic substrate is the bottleneck of the high-density packaging. A silicon interposer with through-silicon vias (TSVs) is commonly used to provide a platform with a high wiring density to redistribute I/Os. After I/O redistribution, larger solder joints with a larger pitch can be used to connect the interposer to the organic substrate. In this paper, a TSV-based silicon interposer with a cavity and copper pillars for 3-D packaging is presented. The cavity hosts the flip-chip device. There are copper-filled TSVs in the cavity to provide the electrical interconnections to the backside of the interposer. Flip-chip solder bumps are electroplated on the copper pillars. Subsequent to the flip-chip assembly process, the device is seated in the cavity entirely. The backside of the flip chip is lower than that of the surface of the interposer. This provides a better environment for further die stacking on the surface of the interposer. The microfabrication process of the proposed silicon interposer with TSVs in cavities is discussed in detail.
ISSN 1530-4388
Language English
Format Article
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