Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/6097

A Low-Noise Monolithic CMOS Bio-Potential Detector

Authors Fung, Sheung Wai
Liu, Bing
Yuan, Jie
Guo, Qing
Issue Date 2009
Source ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, p. 653-656
Summary Bio-potential detection is important for bio-medical diagnostics and research. Bio-potentials are generally weak (mu V) with high offsets (100mV level). Low noise processing is critical to extract the signal. In this paper, we report the design of a single-chip CMOS bio-potential detector. The design uses chopping to suppress the low-frequency noise in CMOS amplifiers. The strong offset is removed by a high gain feedback loop with a low pass filter with 1Hz cut-off frequency. A high-gain front stage is designed to further suppress the noise. The nonlinearity in the high-gain front stage can be compensated by calibration. A chopping-pulse free switched-capacitor low-pass filter follows for variable gain amplification and noise bandwidth limiting. The circuit is designed in a 0.35 mu m CMOS process for 50 mu V-10mV bio-potentials with offset up to 100mV. HSPICE simulations verify that the designed detector achieve the gain of 400 and 4000. The selectable bandwidth is 1kHz for EEG/ECG/EMG or 5kHz for extra-cellular recording. The design does not require external capacitors. The in-band noise is lower than 58nV/Hz(0.5). The power consumption of the detector is less than 160 mu W. The die area is 0.3mmx0.7mm.
Subjects
ISSN 0271-4310
ISBN 978-1-4244-3827-3
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Language English
Format Conference paper
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