A single-chip UHF RFID reader in 0.18 mu m CMOS process
Chui, Kay W. C.
Lok, Chi Fung
Luong, Howard C.
Lau, Vincent K.
|Source||IEEE journal of solid-state circuits, v. 43, (8), 2008, AUG, p. 1741-1754|
|Summary||A single-chip UHF RFID reader that integrates all building blocks-including an RF transceiver, IQ data converters, and a digital baseband-is implemented in a 0.18 mu m CMOS process. A high-linearity RX front-end and a low-phase-noise synthesizer are proposed to handle the large self-interferer, which is a key challenge in the reader RX design. Highly reconfigurable mixed-signal baseband architecture for channel-selection filtering is proposed to achieve power optimization for multi-protocol operation with different system dynamic ranges and data rates. The reader dissipates a maximum power of 276.4 mW when transmitting maximum output power of 10.4 dBm and receiving the tag's response of -70 dBm in the presence of -5 dBm self-interferer while occupying 18.3 mm(2).|
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