||Driven by the ever-increasing demand for higher data rate, lower cost and lower power consumption in wireless systems, wireless transceivers have gone through a dramatic evolution over the past decade. CMOS technology has become more and more attractive due to its potential in implementing high-speed and low-cost integrated systems for commercial RF applications, such as GSM, Wireless LAN, Bluetooth, Ultra-wide band (UWB), Radio-Frequency Identification (RFID), etc. With the rapid device downscaling and the growing need to reduce the power consumption of digital circuits, RF and analog circuits implemented in CMOS technology have been increasingly demanded for lower supply voltage and lower power consumption design. Furthermore, in order to achieve higher data rates, wireless applications have been continuously increasing the operation frequency and bandwidth. Frequency divider, as a critical building block in a frequency synthesizer for clock signal generation, is thus required to operate at higher frequency from a lower supply voltage with lower power consumption. In this thesis, the design of ultra-low-voltage high-frequency CMOS transformer-feedback frequency divider is investigated and demonstrated. The first design is an ultra-low-voltage (ULV) transformer-coupled (TC) divide-by-2 frequency divider. On-ship transformers are used to cross-couple two regenerative dividers to achieve not only quadrature-phase generation but also low-voltage, low-power and wideband operation. Implemented in 0.13-μm CMOS technology and operating at a 0.55V supply voltage, the ULV-TC divider measures an input operation range of 19.2% from 22.6GHz to 27.4GHz and an IQ sideband rejection of 41dB with a minimum power consumption of 6.8mW. The second design is an ultra-low-voltage (ULV) transformer-feedback (TF) divide-by-3 frequency divider. A novel regenerative division loop is proposed for realizing high division ratio and on-chip transformers are used for feedback and low-voltage, low-power operation.