||Fast-load transient response DC-DC power converters are currently in great demand for portable electronic devices. Conventional control methodologies such as voltage-mode and current-mode scheme cannot achieve fast-load transient response due to the large compensation capacitor existing in the feedback control loop. In recent years, V2 control scheme has been proposed and proved to achieve fast-load transient response. It uses a relatively large equivalent series resistance (ESR) value of the output capacitor to create large output ripple for the control signal to enhance the load transient response. However, this ripple voltage is too large and not desirable in many applications. In addition, the stability of V2 control highly relies on many other parameters in the control circuitry and power stage. In this thesis, V2 control buck converter has been analyzed in time domain. Besides the normal PWM operation and sub-harmonic oscillation regions (when duty cycle > 0.5), one special operation region was discovered and identified as Improper PWM operation. This operation region is stable but has a relatively large output ripple voltage. The conditions for these three operation regions has been analyzed and concluded with a single quadratic equation. Based on this developed mathematical model, a novel on-chip control scheme is proposed and implemented with a DC-DC buck converter. The proposed converter can achieve the same fast-load transient response as V2 control without relying on the ESR value of the output capacitor. In addition, the proposed scheme has better switching noise compatibility due to the fact that a large compensation ramp magnitude can be used. The proposed schemes have been implemented on a buck converter with AMS 0.35μm CMOS technology. The mathematical model representing the three operation regions in V2 control and the proposed fast-load transient response circuit with small ESR value has been verified with experimental results.