Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/74665

Failure Analysis and Experimental Verification for Through-Silicon-via Underfill Dispensing on 3-D Chip Stack Package

Authors Le, Fuliang HKUST affiliated (currently or previously)
Lee, Shi Wei Ricky View this author's profile
Lo, Chi Chuen HKUST affiliated (currently or previously)
Yang, Chaoran HKUST affiliated (currently or previously)
Issue Date 2015
Source IEEE Transactions on Components, Packaging and Manufacturing Technology , v. 5, (10), October 2015, p. 1525-1532
Summary In this paper, through-silicon-via (TSV) dispensing is introduced to address the underfill challenge for a 3-D chip stack package. An edge flood failure would form if the underfill flow breaks through the planar sidewalls of a 3-D package. The edge flood failure could lead to an incomplete underfill and the occupation of a huge area on the substrate. In order to avoid an edge flood, the encapsulant pressure around the chip edges cannot exceed the limit equilibrium pressure. The TSVs in the stacked chips should be aligned in the vertical direction, because this aligned configuration has the lowest risk of forming an edge flood. In order to find a tradeoff between the short filling time and the low risk of forming an edge flood, an optimized TSV pattern, including central and outer TSVs, is proposed for the underfill of a 3-D chip stack package. The central TSVs allow a constant flow rate to obtain a fast filling effect. The outer TSVs allow free droplets to eliminate the potential edge flood during the underfilling of the area around the chip edges. The test vehicle was a four-layer die/interposer stack package. The effect of the TSV underfill was inspected by acoustic scanning and cross sectioning. The inspection results showed that the underfill was completed without voids and the solder joints were well covered by the encapsulant.
Subjects
ISSN 2156-3950
Language English
Format Article
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