Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/7551

Low power and compact digital pixel image sensor using multiple sampling scheme

Authors Wu, Xiajun
Issue Date 2009
Summary CMOS image sensors are widely used in many electronic devices such as smart phone and digital camera because of their easy integration with standard CMOS process. Recently, the aggressive technology scaling of CMOS process has open the door to the implementation of pixel-level analog to digital data conversion, leading to the digital pixel sensor (DPS). Although DPS features advantages such as wide dynamic range and immunity to technology scaling, conventional DPS still has two major problems waiting to be solved. Firstly, the power consumption is still relatively large since each pixel includes an analog comparator consuming static power. Secondly, large pixel size is another issue of digital pixel sensor due to a typical 8 bits pixel-level memory for data storage. This thesis proposes two solutions to solve these two problems. A low power CMOS image sensor using DPS scheme is proposed. A sub-threshold control unit is used in order to enable or disable the pixel-level ADC depending on the photodiode sensing voltage, hence enabling to save the static power needed to operate the pixel-level ADC. Results show that up to 90% power saving is achieved when compared with the conventional digital pixel sensor. In addition, a compact digital pixel sensor employing time to spike analog to digital conversion is presented. Different from conventional digital pixel sensor using 8 bit in-pixel memory, the proposed scheme efficiently utilizes the characteristics of timing information provided by the timing control unit and partitions the data write operation into 8 phases such that 7 bit in-pixel memory can be moved out of pixel featuring 87.5% saving of the in-pixel memory. The conditional refreshment scheme is employed to avoid proportionally increasing the exposure time while increasing the resolution enabling better speed performance for high resolution applications. The dual sampling memory is designed to flexibly accommodate different encoding schemes. Results show that up to 75% pixel area saving is achieved compared with the conventional digital pixel sensor. Additionally, analysis and simulation results show that the dynamic range can be extended to be larger than 100dB. The proposed technique achieves 23μm × 21μm pixel size with a 23% fill factor in a 0.35μm CMOS process.
Note Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2009
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Language English
Format Thesis
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