Please use this identifier to cite or link to this item: http://hdl.handle.net/1783.1/7575

Link faults analysis and fault tolerant techniques on network-on-chip system

Authors Teh, Ying Fei
Issue Date 2012
Summary With reducing feature size of transistors and increasing number of cores on a single chip, system-on-chips (SoCs) are becoming more vulnerable to faults due to the physical level defects of VLSI fabrication. Fault tolerance and reliability have become two significant challenges for SoC designers. In this work, we have introduced analytical model for each link fault handling schemes in interest based on queuing theory to estimate the performance, and thus assist the designers to determine the best scheme to be used under different traffic condition. The shortcoming of the link fault handling schemes are found through analytical method and simulation method, and thus we propose a novel and efficient scheme to handle the faulty links of a network-on-chip (NoC) by adaptively combining the two fault link handling schemes, namely the link sharing scheme and partial fault link utilization scheme. With our approach, the system is able to optimize the usage of the remaining bandwidth of the links under different fault conditions. The scheme has been optimized to be able to utilize bi-directional NoC capability as well. Through Noxim simulations, the results show a significant improvement in average latency and maximum delay by using the proposed combined scheme under different traffics compared to the two schemes. Our proposed scheme offers an efficient way to supplement current available fault handling scheme to increase the effective yield of large and complex NoC systems by enabling the usage of faulty chip with compromise in the latency performance.
Note Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2012
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Language English
Format Thesis
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