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Wire sweep study of package array mold during transfer molding process

Authors Han, Jiale
Issue Date 2012
Summary In order to maximize production rate, an increasing number of electronic packages are manufactured in a package array mold, such as Small Outline Transistor (SOT) package. Due to the complicated structure design of the package and mold cavity, wire sweep is becoming a severe problem. In the study, the numerical model was firstly validated by experimental work using short shots experiment and X-ray technology. Then the verified model was employed for flow pattern and wire sweep analysis. The leadframe detail structure effects were evaluated at first. The effects of leadframe detail structure on flow pattern and wire sweep are insignificant and may be ignored, most likely due to the thin thickness of leadframe and the relatively lower position to the bond wire loop. Besides, for fixed width and length of the die, the wire sweep behavior was predicted by simulation to estimate the influence of the die height (thickness). The results show that the thinner the die, the smaller the wire sweep. Furthermore, the effect of cavity height on wire sweep value was also evaluated. Then, the ratio of the die height to that of the cavity was introduced as an index to investigate the main factors which influence the wire sweep values and propose a guideline for package and cavity design to reduce the wire sweep. It can be further concluded that velocity is more sensitive to the change of the package and cavity structures, compared with the viscosity. Next, a new design of industry package array mold was introduced for wire sweep study with the practical transfer molding process conditions. It shows the sharply increased velocity is the essential reason for the wire sweep issue at the vent side of the mold, due to the unbalanced flow of EMC. In order to address the issue, the transfer mold process optimization with transfer profile was carried out. The simulation results reveal the transfer molding process optimization is an effective and convenient way to deal with the wire sweep problem. Furthermore, the flow pattern optimization was carried out to fulfill the balance flow of EMC by changing the mold design to lower wire sweep risk.
Note Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2012
Language English
Format Thesis
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