||One time programmable memory (OTP) is always an important part in integrated circuits and/or electronic devices. Its applications include secure key storage, implantable medical devices, RFID, handheld wireless communication devices, analog trimming, code storage, encryption keys etc. Conventionally, most of the OTP is fabricated using either special processes which require additional masks to the standard CMOS process, or some processes which are even not CMOS compatible. This complicates the integration process between circuit and memory design, as separate packaging is expected. This will increase the design time and process cost, which may even lead to monetary losses. In which case, OTP design in standard CMOS process becomes prevalent as it offers a simple and reliable OTP memory solution, which requires no additional masks during fabrication, for highly competitive product designs. In this thesis, three different memory cell architectures are proposed to address the challenges of designing OTP in standard CMOS process without additional masks. Based on the conventional three transistors OTP memory cell array architecture, a two transistors memory cell array solution is proposed. Another OTP memory cell array, which uses diode as the driving device, is also proposed. Finally, a novel contact fuse OTP memory cell is presented. All three proposed memory designs realize much reduced area reduction when compared with the conventional three-transistor OTP architecture. In order to verify the design functionalities, they are all fabricated using standard 0.18μm CMOS technology. Measurement results and performance comparisons between the conventional OTP design and the proposed designs will be presented.